Invention Grant
US07307885B2 Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit 有权
配有参考电池和负载平衡电路的多值非易失性半导体存储器件

Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit
Abstract:
A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.
Public/Granted literature
Information query
Patent Agency Ranking
0/0