Invention Grant
US07307885B2 Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit
有权
配有参考电池和负载平衡电路的多值非易失性半导体存储器件
- Patent Title: Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit
- Patent Title (中): 配有参考电池和负载平衡电路的多值非易失性半导体存储器件
-
Application No.: US11063999Application Date: 2005-02-24
-
Publication No.: US07307885B2Publication Date: 2007-12-11
- Inventor: Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
- Applicant: Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Arent Fox, LLP
- Main IPC: G11C16/28
- IPC: G11C16/28

Abstract:
A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.
Public/Granted literature
- US20050162955A1 Nonvolatile semiconductor memory device Public/Granted day:2005-07-28
Information query