- 专利标题： Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation
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申请号： US10837596申请日： 2004-05-04
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公开(公告)号： US07148572B2公开(公告)日： 2006-12-12
- 发明人: Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
- 申请人： Shinichi Domae , Hiroshi Masuda , Yoshiaki Kato , Kousaku Yano
- 申请人地址： JP Osaka
- 专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人： Matsushita Electric Industrial Co., Ltd.
- 当前专利权人地址： JP Osaka
- 代理机构： McDermott Will & Emery LLP
- 优先权： JP9-186140 19970711; JP9-348965 19971218
- 主分类号： H01L23/48
- IPC分类号： H01L23/48 ; H01L23/52 ; H01L29/40
摘要：
A multilayer wiring structure of a semiconductor device having a stacked structure is arranged to restrain reliability degradation due to stress applied to the region of wiring between opposite upper and lower plugs. The rate of overlap of contact surface between upper plug and wiring on contact surface between lower plug and wiring, is small to the extent that no void is generated. The multilayer wiring structure is produced such that no grain boundary is contained in the region of wiring between upper and lower plugs. The difference in thermal expansion coefficient between the material of wiring and the material of upper and lower plugs, is small to the extent that no void is generated.
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