A clock selection circuit includes an output multiplexer, control logic, and edge detection logic. The multiplexer includes inputs to receive multiple input clock signals, an output to generate the output clock signal, and a control terminal to receive a synchronized clock select signal. The control logic includes a first input to receive a clock select signal, a second input to receive a first control clock signal, a third input to receive a synchronization signal, and an output to selectively update the synchronized clock select signal with transitions in the clock select signal. The edge detection logic includes first inputs to receive the multiple input clock signals, a second input to receive a second control clock signal, and an output to generate the synchronization signal.