发明授权
US06869337B2 System and method for polishing and planarizing semiconductor wafers using reduced surface area polishing pads and variable partial pad-wafer overlapping techniques
失效
使用减小的表面积抛光垫和可变部分焊盘 - 晶片重叠技术来研磨和平坦化半导体晶片的系统和方法
- 专利标题： System and method for polishing and planarizing semiconductor wafers using reduced surface area polishing pads and variable partial pad-wafer overlapping techniques
- 专利标题（中）： 使用减小的表面积抛光垫和可变部分焊盘 - 晶片重叠技术来研磨和平坦化半导体晶片的系统和方法
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申请号： US10770599申请日： 2004-02-03
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公开(公告)号： US06869337B2公开(公告)日： 2005-03-22
- 发明人: John M. Boyd , Yehiel Gotkis , Rod Kistler
- 申请人： John M. Boyd , Yehiel Gotkis , Rod Kistler
- 申请人地址： US CA Fremont
- 专利权人： Lam Research Corporation
- 当前专利权人： Lam Research Corporation
- 当前专利权人地址： US CA Fremont
- 代理机构： Brinks Hofer Gilson & Lione
- 主分类号： B24B37/04
- IPC分类号： B24B37/04 ; B24B37/26 ; B24B49/04 ; B24B51/00 ; B24B53/007 ; B24B53/017 ; H01L21/304 ; B24B1/00
摘要：
A system and method for polishing semiconductor wafers includes a variable partial pad-wafer overlap polisher having a reduced surface area, fixed-abrasive polishing pad and a polisher having a non-abrasive polishing pad for use with an abrasive slurry. The method includes first polishing a wafer with the variable partial pad-wafer overlap polisher and the fixed-abrasive polishing pad and then polishing the wafer in a dispersed-abrasive process until a desired wafer thickness is achieved.
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