Invention Grant
- Patent Title: Semiconductor device having doped polycrystalline layer
- Patent Title (中): 具有掺杂多晶层的半导体器件
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Application No.: US17672Application Date: 1998-02-03
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Publication No.: US5932893APublication Date: 1999-08-03
- Inventor: Akiharu Miyanaga , Hisashi Ohtani , Satoshi Teramoto
- Applicant: Akiharu Miyanaga , Hisashi Ohtani , Satoshi Teramoto
- Applicant Address: JPX Kanagawa
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JPX Kanagawa
- Priority: JPX5-166117 19930612
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/02 ; H01L21/324 ; H01L21/336 ; H01L21/77 ; H01L21/82 ; H01L21/84 ; H01L27/02 ; H01L27/12 ; H01L29/02 ; H01L29/78 ; H01L29/786 ; H01L49/00 ; H01L29/76
Abstract:
An insulated gate field effect transistor comprises a silicon channel region. The silicon is crystallized by heat annealing while a suitable metal element such as nickel helps the crystallization. The crystallization proceeds in the silicon film laterally from the portion where the nickel is directly introduced. The TFT is arranged in such a manner that the source-drain direction of the TFT is aligned with the direction of the crystal growth or intersects with the crystal growth direction at a desired direction.
Public/Granted literature
- US5349304A Operational amplifier having multiple positive inputs Public/Granted day:1994-09-20
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