In a mask ROM device, a plurality of recesses extending parallel to each other are formed in a memory cell array region on the surface of a silicon substrate. In the direction intersecting the recesses, first and second transistor trains are formed in which select transistors and memory transistors are connected in series. The MOS transistors of the transistor trains have the sidewall of recess 5 formed as a channel region. A depletion implantation layer corresponding to data to be stored is formed on the sidewall of the recess. The first transistor train and the second transistor train are insulated and isolated from each other by an LOCOS isolation film.