发明授权
- 专利标题: Output circuit with buffer
- 专利标题(中): 输出电路带缓冲器
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申请号: US960872申请日: 1992-10-14
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公开(公告)号: US5289063A公开(公告)日: 1994-02-22
- 发明人: Yukihisa Orisaka , Junji Tanaka , Yoshiki Sano
- 申请人: Yukihisa Orisaka , Junji Tanaka , Yoshiki Sano
- 申请人地址: JPX Osaka
- 专利权人: Sharp Kabushiki Kaisha
- 当前专利权人: Sharp Kabushiki Kaisha
- 当前专利权人地址: JPX Osaka
- 优先权: JPX3-295018 19911014
- 主分类号: H03K17/16
- IPC分类号: H03K17/16 ; H03K17/04 ; H03K17/687 ; H03K19/017 ; H03K19/0175 ; H03K19/096
摘要:
An output circuit having a buffer, the buffer including the first transistor which receives at a gate thereof a periodic input voltage and the second transistor, the first and the second transistors being connected in series across a power line and a ground line, a junction of the first and second transistors being connected to an output terminal. The output circuit includes a circuit for applying, to a gate of the second transistor, a first voltage for the second transistor to serve as a bias transistor for charging a load connected to the output terminal with a voltage corresponding to the input voltage, and the second voltage greater than the first voltage for the second transistor to serve as a discharge transistor for discharging the load.
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