发明授权
- 专利标题: Logic circuit having a test data scan circuit
- 专利标题(中): 具有测试数据扫描电路的逻辑电路
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申请号: US810296申请日: 1985-12-18
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公开(公告)号: US4703257A公开(公告)日: 1987-10-27
- 发明人: Takao Nishida , Toru Hiyama , Kaoru Moriwaki , Shun Ishiyama , Shunsuke Miyamoto
- 申请人: Takao Nishida , Toru Hiyama , Kaoru Moriwaki , Shun Ishiyama , Shunsuke Miyamoto
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX59-270877 19841224
- 主分类号: G01R31/3185
- IPC分类号: G01R31/3185 ; G01R31/28
摘要:
A logic circuit having a diagnostic function is disclosed in which each of first latches for applying data to combinational circuits included in the logic circuit and/or receiving data from the combinational circuits is provided with a second latch and a selector for selecting the output of the first latch in a first mode and for selecting the output of the second latch in a second mode. In a regular operation, the output of the first latch is never transferred through the second latch, and the selector is operated in the first mode. Accordingly, the output of the first latch is supplied directly to a succeeding combinational circuit, and thus the delay caused by the second latch in the prior art can be eliminated. Although the delay caused by the selector is unavoidable, this delay can be made far smaller than the delay caused by the second latch. In a diagnostic operation, the output of the first latch is transferred through the second latch, and the selector is operated in the second mode, in order to perform the diagnostic operation stably even when data is transferred between first latches having the same phase, or the logic circuit includes a one-latch loop.
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