Invention Application
- Patent Title: IN-SITU FORMATION OF METAL GATE MODULATORS
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Application No.: US18783632Application Date: 2024-07-25
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Publication No.: US20240379448A1Publication Date: 2024-11-14
- Inventor: Hsin-Han Tsai , Chung-Chiang Wu , Cheng-Lung Hung , Weng Chang , Chi On Chui
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/28 ; H01L27/088 ; H01L29/49

Abstract:
A method includes forming a gate dielectric on a semiconductor region, depositing a work-function layer over the gate dielectric, depositing a silicon layer over the work-function layer, and depositing a glue layer over the silicon layer. The work-function layer, the silicon layer, and the glue layer are in-situ deposited. The method further includes depositing a filling-metal over the glue layer; and performing a planarization process, wherein remaining portions of the glue layer, the silicon layer, and the work-function layer form portions of a gate electrode.
Information query
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