Invention Publication
- Patent Title: POST-PROGRAM ERASE IN 3D NAND
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Application No.: US18358635Application Date: 2023-07-25
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Publication No.: US20240296891A1Publication Date: 2024-09-05
- Inventor: Ming Wang , Liang Li , Xuan Tian
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: G11C16/16
- IPC: G11C16/16 ; G11C16/04 ; G11C16/08 ; G11C16/10

Abstract:
Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.
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