Invention Publication
- Patent Title: LOW RESISTANCE CROSSPOINT ARCHITECTURE
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Application No.: US18409413Application Date: 2024-01-10
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Publication No.: US20240224825A1Publication Date: 2024-07-04
- Inventor: Rajasekhar Venigalla , Patrick M. Flynn , Josiah Jebaraj Johnley Muthuraj , Efe Sinan Ege , Kevin Lee Baker , Tao Nguyen , Davis Weymann
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- The original application number of the division: US17468167 2021.09.07
- Main IPC: H10N70/00
- IPC: H10N70/00 ; G11C13/00 ; H01L21/768 ; H01L23/522 ; H01L23/528 ; H10B63/00 ; H10N70/20

Abstract:
Methods, systems, and devices for a low resistance crosspoint architecture are described. A manufacturing system may deposit a thermal barrier material, followed by a first layer of a first conductive material, on a layered assembly including a patterned layer of electrode materials and a patterned layer of a memory material. The manufacturing system may etch a first area of the layered assembly to form a gap in the first layer of the first conductive material, the thermal barrier material, the patterned layer of the memory material, and the patterned layer of electrode materials. The manufacturing system may deposit a second conductive material to form a conductive via in the gap, where the conductive via extends to a height within the layered assembly that is above the thermal barrier material.
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