- 专利标题: Packaging Structures for Electronic elements and Solid Electrolytic Capacitor Elements and Methods thereof
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申请号: US17667568申请日: 2022-02-09
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公开(公告)号: US20230253162A1公开(公告)日: 2023-08-10
- 发明人: Yu-Peng Chung , Chia-Wei Li , Che-Chih Tsao
- 申请人: Yu-Peng Chung , Chia-Wei Li , Che-Chih Tsao
- 申请人地址: TW New Taipei City
- 专利权人: Yu-Peng Chung,Chia-Wei Li,Che-Chih Tsao
- 当前专利权人: Yu-Peng Chung,Chia-Wei Li,Che-Chih Tsao
- 当前专利权人地址: TW New Taipei City
- 主分类号: H01G9/26
- IPC分类号: H01G9/26 ; H01G9/15 ; H01G9/08
摘要:
This invention describes packaging structures and methods for electronic devices, especially for solid electrolytic capacitor devices. A packaging structure applies at least two protective substrates to sandwich one or multiple capacitor elements stacked together in between with an insulating material surrounding the capacitor elements also in between the protective substrates. Each protective substrate comprises an anodic conductor pad and a cathodic conductor pad. The anodic conductor pad is electrically connected to an external anode terminal, which is in turn electrically connected to the tip face of the anode end of the capacitor element. The cathodic pad is electrically connected to the cathode of the capacitor element as well as to an external cathode terminal. For quantity production, the basic concept includes sandwiching hundreds of capacitor elements in between large thin protective substrates and bonding them to the conductor pads on the protective substrates; then filling in the insulating material by a capillary filling process; then curing the assembly into a first intermediate assembly. A second intermediate assembly is then made by cutting slots over the first intermediate assembly to expose the anodic and cathodic ends of each capacitor device for subsequent metal depositions to make the external terminals.
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