Invention Application
- Patent Title: FABRICATION PROCESS COMPRISING AN OPERATION OF DEFINING AN EFFECTIVE CHANNEL LENGTH FOR MOSFET TRANSISTORS
-
Application No.: US16939767Application Date: 2020-07-27
-
Publication No.: US20210036126A1Publication Date: 2021-02-04
- Inventor: Julien Delalleau , Franck JULIEN
- Applicant: STMicroelectronics (Rousset) SAS
- Applicant Address: FR Rousset
- Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee: STMicroelectronics (Rousset) SAS
- Current Assignee Address: FR Rousset
- Priority: FR1908778 20190731,EP20186529.2 20200717
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/10 ; H01L21/8234 ; H01L21/027 ; H01L29/78

Abstract:
In fabricating metal-oxide-semiconductor field-effect transistors (MOSFETs), the implanting of lightly doped drain regions is performed before forming gate regions with a physical gate length that is associated with a reference channel length. The step of implanting lightly doped drain regions includes forming an implantation mask defining the lightly doped drain regions and an effective channel length of each MOSFET. The forming of the implantation mask is configured to define an effective channel length of at least one MOSFET that is different from the respective reference channel length.
Public/Granted literature
- US11424342B2 Fabrication process comprising an operation of defining an effective channel length for MOSFET transistors Public/Granted day:2022-08-23
Information query
IPC分类: