Invention Application
- Patent Title: Latency-Optimized Mechanisms for Handling Errors or Mis-Routed Packets for Computer Buses
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Application No.: US17031822Application Date: 2020-09-24
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Publication No.: US20210013999A1Publication Date: 2021-01-14
- Inventor: Swadesh Choudhary , Debendra Das Sharma , Mahesh Wagh
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H04L1/00
- IPC: H04L1/00 ; H04L12/833

Abstract:
Systems and devices can include protocol stack circuitry to perform certain methods, including receiving a flow control unit (flit) header and a transaction layer packet (TLP) payload, the TLP payload comprising a first portion and a second portion, determining that the flit header is free from errors, forwarding the flit header and the first portion of the TLP payload to a link partner based on the flit header being free from errors, identifying that the flit contains an error from the second portion of the TLP payload, and sending a data link layer packet (DLLP) to the link partner to indicate the error in the TLP payload.
Information query