Invention Application
- Patent Title: METHOD OF FORMING SEMICONDUCTOR STRUCTURE WITH ALIGNING MARK
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Application No.: US15487396Application Date: 2017-04-13
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Publication No.: US20170221834A1Publication Date: 2017-08-03
- Inventor: Ying-Chiao Wang , Yu-Hsiang Hung , Chao-Hung Lin , Ssu-I Fu , Chih-Kai Hsu , Jyh-Shyang Jenq
- Applicant: UNITED MICROELECTRONICS CORP.
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L21/28 ; H01L21/033 ; H01L21/311

Abstract:
The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same.
Public/Granted literature
- US09960123B2 Method of forming semiconductor structure with aligning mark in dicing region Public/Granted day:2018-05-01
Information query
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