Invention Application
- Patent Title: INSTRUCTION AND LOGIC TO PROVIDE VECTOR LOADS AND STORES WITH STRIDES AND MASKING FUNCTIONALITY
- Patent Title (中): 指示和逻辑提供矢量负载和存储带有条件和屏蔽功能
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Application No.: US13977730Application Date: 2011-09-26
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Publication No.: US20140195775A1Publication Date: 2014-07-10
- Inventor: Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Suleyman Sair , Charles R. Yount
- Applicant: Elmoustapha Ould-Ahmed-Vall , Kshitij A. Doshi , Suleyman Sair , Charles R. Yount
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- International Application: PCT/US11/53321 WO 20110926
- Main IPC: G06F9/30
- IPC: G06F9/30

Abstract:
Instructions and logic provide vector loads and/or stores with stride and mask functionality. Some embodiments, responsive to an instruction specifying: a set of loads, destination register, mask register, memory address, and stride length; execution units read values in the mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the corresponding multiple of said stride length is generated according to the data field's position in the mask register to load the data element from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. These instructions can restart after faults.
Public/Granted literature
- US09672036B2 Instruction and logic to provide vector loads with strides and masking functionality Public/Granted day:2017-06-06
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