Reverse Partial Etching Scheme for Magnetic Device Applications

Invention Application

US20130244342A1 Reverse Partial Etching Scheme for Magnetic Device Applications 有权

Title translation: 磁性器件应用的反向部分蚀刻方案

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Patent Title: Reverse Partial Etching Scheme for Magnetic Device Applications
Patent Title (中): 磁性器件应用的反向部分蚀刻方案
Application No.: US13419507

Application Date: 2012-03-14
Publication No.: US20130244342A1

Publication Date: 2013-09-19
Inventor: Yu-Jen WANG , Yuan-Tung CHIN
Applicant: Yu-Jen WANG , Yuan-Tung CHIN
Applicant Address: US CA Milpitas
Assignee: HEADWAY TECHNOLOGIES, INC.
Current Assignee: HEADWAY TECHNOLOGIES, INC.
Current Assignee Address: US CA Milpitas
Main IPC: H01L21/8246
IPC: H01L21/8246

Reverse Partial Etching Scheme for Magnetic Device Applications

Abstract:

A magnetic tunnel junction (MTJ) structure is provided over a device wherein the MTJ comprises a tunnel barrier layer between a free layer and a pinned layer; and a top and bottom electrode inside the MTJ structure. A hard mask layer is formed on the top electrode. The hard mask layer, top electrode, free layer, tunnel barrier layer, and pinned layer are patterned to define the magnetic tunnel junction (MTJ) structures. A first dielectric layer is deposited over the MTJ structures and planarized to expose the top electrode. Thereafter, the top electrode and free layer are patterned. A second dielectric layer is deposited over the MTJ structures and planarized to expose the top electrode. A third dielectric layer is deposited over the MTJ structures and a metal line contact is formed through the third dielectric layer to the top electrode to complete fabrication of the magnetic device.

Abstract(Chinese):

在一个器件上提供一个磁性隧道结（MTJ）结构，其中MTJ包括在自由层和钉扎层之间的隧道势垒层; 以及MTJ结构内的顶部和底部电极。在顶部电极上形成硬掩模层。将硬掩模层，顶电极，自由层，隧道势垒层和钉扎层图案化以限定磁隧道结（MTJ）结构。第一电介质层沉积在MTJ结构上并且被平坦化以暴露顶部电极。此后，对顶部电极和自由层进行图案化。第二电介质层沉积在MTJ结构上并且被平坦化以暴露顶部电极。在MTJ结构上沉积第三电介质层，并且通过第三电介质层形成金属线接触到顶部电极以完成磁性器件的制造。

Public/Granted literature

US08748197B2 Reverse partial etching scheme for magnetic device applications Public/Granted day:2014-06-10

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IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8246	.........只读存储器结构（ROM）