Invention Application
- Patent Title: CURRENT MIRROR CIRCUIT
- Patent Title (中): 当前镜像电路
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Application No.: US13046953Application Date: 2011-03-14
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Publication No.: US20110304387A1Publication Date: 2011-12-15
- Inventor: Kenichi Hirashiki , Norio Hagiwara , Tsutomu Nakashima , Minoru Nagata
- Applicant: Kenichi Hirashiki , Norio Hagiwara , Tsutomu Nakashima , Minoru Nagata
- Applicant Address: JP Tokyo
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Tokyo
- Priority: JPP2010-134949 20100614
- Main IPC: G05F1/10
- IPC: G05F1/10

Abstract:
In one embodiment, a current mirror circuit includes first to fourth insulated gate field effect transistors (FETs), and a bias circuit. The gate electrodes of the first and second FETs are connected to each other. The source electrode of the third FET is connected to the drain electrode of the first FET, and the drain electrode of the third FET is connected to the gate electrodes of the first and second FETs and a current input terminal. The gate electrode of the fourth FET is connected to the gate electrode of the third FET, the source electrode of the fourth FET is connected to the drain electrode of the second FET, and the drain electrode of the fourth FET becomes a current output terminal. The bias circuit is configured to provide a bias voltage to the gate electrodes of the third and fourth FETs.
Public/Granted literature
- US08456227B2 Current mirror circuit Public/Granted day:2013-06-04
Information query
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