Invention Application
- Patent Title: SEMICONDUCTOR DIE PACKAGE INCLUDING EXPOSED CONNECTIONS
- Patent Title (中): 半导体封装包括暴露的连接
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Application No.: US12044314Application Date: 2008-03-07
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Publication No.: US20090224383A1Publication Date: 2009-09-10
- Inventor: Erwin Victor Cruz , Maria Cristina Estacio
- Applicant: Erwin Victor Cruz , Maria Cristina Estacio
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L21/60
Abstract:
A clip structure and semiconductor die package. The clip structure includes a first portion and a second portion, with a connecting structure located between the first and second portion. The clip structure is substantially planar. The semiconductor die package includes a semiconductor die located between a leadframe structure and a clip structure. Slots are formed within the molding material covering portions of the semiconductor die package. The slots are located between a first portion and the second portion of the clip structure, and the slot overlap with the semiconductor die.
Public/Granted literature
- US07972906B2 Semiconductor die package including exposed connections Public/Granted day:2011-07-05
Information query
IPC分类:
