- 专利标题： Gate resistive ladder bypass for RF FET switch stack
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申请号： US18183806申请日： 2023-03-14
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公开(公告)号： US12119814B2公开(公告)日： 2024-10-15
- 发明人: Ravindranath D. Shrivastava , Alper Genc
- 申请人： pSemi Corporation
- 申请人地址： US CA San Diego
- 专利权人： pSemi Corporation
- 当前专利权人： pSemi Corporation
- 当前专利权人地址： US CA San Diego
- 代理机构： Steinfl + Bruno LLP
- 主分类号： H03K17/16
- IPC分类号： H03K17/16 ; H03K17/041 ; H03K17/0412 ; H03K17/06 ; H03K17/687 ; H03K17/693 ; H04B1/44 ; H01L27/06
摘要：
A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.
公开/授权文献
- US20230283277A1 GATE RESISTIVE LADDER BYPASS FOR RF FET SWITCH STACK 公开/授权日：2023-09-07
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