Invention Grant
- Patent Title: Formation of metal vias on metal lines
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Application No.: US17184020Application Date: 2021-02-24
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Publication No.: US12113020B2Publication Date: 2024-10-08
- Inventor: Ryan Scott Smith , Kai Wu , Nicolas Louis Gabriel Breil
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L23/532
- IPC: H01L23/532 ; H01L21/02 ; H01L21/768 ; H01L23/522 ; H01L23/528

Abstract:
Exemplary semiconductor processing methods include forming a via in a semiconductor structure. The via may be defined in part by a bottom surface and a sidewall surface formed in the semiconductor structure around the via. The methods may also include depositing a tantalum nitride (TaN) layer on the bottom surface of the via. In embodiments, the TaN layer may be deposited at a temperature less than or about 200° C. The methods may still further include depositing a titanium nitride (TiN) layer on the TaN layer. In embodiments, the TiN layer may be deposited at a temperature greater than or about 300° C. The methods may additionally include depositing a fill-metal on the TiN layer in the via. In embodiments, the metal may be deposited at a temperature greater than or about 300° C.
Public/Granted literature
- US20220270979A1 FORMATION OF METAL VIAS ON METAL LINES Public/Granted day:2022-08-25
Information query
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