- 专利标题： Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same
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申请号： US18314938申请日： 2023-05-10
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公开(公告)号： US12047095B2公开(公告)日： 2024-07-23
- 发明人: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
- 申请人： Electronics and Telecommunications Research Institute
- 申请人地址： KR Daejeon
- 专利权人： Electronics and Telecommunications Research Institute
- 当前专利权人： Electronics and Telecommunications Research Institute
- 当前专利权人地址： KR Daejeon
- 代理机构： NSIP Law
- 优先权： KR 20150028064 2015.02.27 KR 20160020854 2016.02.22
- 主分类号： H03M13/15
- IPC分类号： H03M13/15 ; H03M13/00 ; H03M13/11 ; H03M13/25 ; H03M13/27 ; H03M13/29
摘要：
A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.
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