- 专利标题: Enhanced channel strain to reduce contact resistance in NMOS FET devices
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申请号: US18106350申请日: 2023-02-06
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公开(公告)号: US12021082B2公开(公告)日: 2024-06-25
- 发明人: Yu-Chang Lin , Chun-Feng Nieh , Huicheng Chang , Hou-Yu Chen , Yong-Yan Lu
- 申请人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 申请人地址: TW Hsinchu
- 专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- 当前专利权人地址: TW Hsinchu
- 代理机构: STUDEBAKER & BRACKETT PC
- 分案原申请号: US14859165 2015.09.18
- 主分类号: H01L27/092
- IPC分类号: H01L27/092 ; H01L21/02 ; H01L21/265 ; H01L21/8234 ; H01L21/8238 ; H01L21/84 ; H01L27/12 ; H01L29/165 ; H01L29/49 ; H01L29/66 ; H01L29/78
摘要:
A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.
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