- 专利标题: Method for evaluating defective region of wafer
-
申请号: US17267566申请日: 2018-12-27
-
公开(公告)号: US11955386B2公开(公告)日: 2024-04-09
- 发明人: Jae Hyeong Lee
- 申请人: SK SILTRON CO., LTD.
- 申请人地址: KR Gumi-si
- 专利权人: SK Siltron Co., Ltd.
- 当前专利权人: SK Siltron Co., Ltd.
- 当前专利权人地址: KR Gumi-si
- 代理机构: KED & Associates LLP
- 优先权: KR 20180096559 2018.08.20
- 国际申请: PCT/KR2018/016723 2018.12.27
- 国际公布: WO2020/040364A 2020.02.27
- 进入国家日期: 2021-02-10
- 主分类号: H01L21/66
- IPC分类号: H01L21/66 ; G01N21/88 ; G01N21/95 ; G01N21/956
摘要:
This embodiment comprises: a step for preparing a sample wafer; a step for forming a first oxide film on the sample wafer at a temperature of 700-800° C.; a step for forming a second oxide film on the first oxide film at a temperature of 800-1000° C.; a step for forming a third oxide film on the second oxide film at a temperature of 1000-1100° C.; a step for forming a fourth oxide film on the third oxide film at a temperature of 1100-1200° C.; a step for removing the first to fourth oxide films; a step for forming a haze on the surface of the sample wafer by etching the sample wafer from which the first to fourth oxide films have been removed; and a step for evaluating a defective region of the sample wafer on the basis of the haze.
公开/授权文献
- US20210320037A1 METHOD FOR EVALUATING DEFECTIVE REGION OF WAFER 公开/授权日:2021-10-14
信息查询
IPC分类: