发明授权
- 专利标题： 3D-interconnect
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申请号： US17340469申请日： 2021-06-07
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公开(公告)号： US11929337B2公开(公告)日： 2024-03-12
- 发明人: Chok J. Chia , Qwai H. Low , Patrick Variot
- 申请人： Invensas LLC
- 申请人地址： US CA San Jose
- 专利权人： Invensas LLC
- 当前专利权人： Invensas LLC
- 当前专利权人地址： US CA San Jose
- 代理机构： HALEY GUILIANO LLP
- 分案原申请号： US15493917 2017.04.21
- 主分类号： H01L21/52
- IPC分类号： H01L21/52 ; H01L21/56 ; H01L23/00 ; H01L23/538 ; H01L25/065 ; H01L23/31 ; H01L23/498 ; H01L25/10
摘要：
A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.
公开/授权文献
- US20210366857A1 3d-Interconnect 公开/授权日：2021-11-25
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