- 专利标题: Compute optimization mechanism for deep neural networks
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申请号: US18168207申请日: 2023-02-13
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公开(公告)号: US11922535B2公开(公告)日: 2024-03-05
- 发明人: Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Jaffery Watson Mendonsa & Hamilton LLP
- 主分类号: G06T1/20
- IPC分类号: G06T1/20 ; G06F9/455 ; G06F9/50 ; G06N3/044 ; G06N3/045 ; G06N3/063 ; G06N3/084 ; G06F8/41
摘要:
Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.
公开/授权文献
- US20230260072A1 COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS 公开/授权日:2023-08-17
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