Invention Grant
- Patent Title: Method of testing an integrated circuit and testing system
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Application No.: US17393232Application Date: 2021-08-03
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Publication No.: US11879933B2Publication Date: 2024-01-23
- Inventor: Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY, LIMITED
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,TSMC NANJING COMPANY, LIMITED
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,TSMC NANJING COMPANY, LIMITED
- Current Assignee Address: TW Hsinchu; CN Nanjing
- Agency: Hauptman Ham, LLP
- Priority: CN 2110752449.3 2021.07.02
- Main IPC: G01R31/02
- IPC: G01R31/02 ; G06F30/398 ; G01R31/317 ; G06F119/08 ; G01R31/28

Abstract:
A method of testing an integrated circuit on a test circuit board includes performing, by a processor, a simulation of a first heat distribution throughout an integrated circuit design, manufacturing the integrated circuit according to the integrated circuit design, and simultaneously performing a burn-in test of the integrated circuit and an automated test of the integrated circuit. The burn-in test has a minimum burn-in temperature of the integrated circuit and a burn-in heat distribution across the integrated circuit. The integrated circuit design corresponds to the integrated circuit. The integrated circuit is coupled to the test circuit board. The integrated circuit includes a set of circuit blocks and a first set of heaters.
Public/Granted literature
- US20230003790A1 METHOD OF TESTING AN INTEGRATED CIRCUIT AND TESTING SYSTEM Public/Granted day:2023-01-05
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