Invention Grant
- Patent Title: Method of manufacturing semiconductor device
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Application No.: US17546275Application Date: 2021-12-09
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Publication No.: US11776924B2Publication Date: 2023-10-03
- Inventor: Chiang-Lin Shih , Pei-Jhen Wu , Ching-Hung Chang , Hsih-Yang Chiu
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agent Xuan Zhang
- The original application number of the division: US16665408 2019.10.28
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L23/00 ; H01L21/768

Abstract:
The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.
Public/Granted literature
- US20220102302A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2022-03-31
Information query
IPC分类: