Invention Grant
- Patent Title: Memory cell array circuit and method of forming the same
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Application No.: US17871144Application Date: 2022-07-22
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Publication No.: US11735263B2Publication Date: 2023-08-22
- Inventor: Chin-I Su , Chung-Cheng Chou , Yu-Der Chih , Zheng-Jun Lin
- Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Hauptman Ham, LLP
- The original application number of the division: US17103239 2020.11.24
- Main IPC: G11C13/00
- IPC: G11C13/00

Abstract:
A method of operating a memory circuit includes generating a first voltage by a first amplifier circuit of a first driver circuit coupled to a first column of memory cells, and generating a first current in response to the first voltage. The first current includes a first set of leakage currents and a first write current. The method further includes generating, by a tracking circuit, a second set of leakage currents configured to track the first set of leakage currents of the first column of memory cells, and mirroring the first current in a first path with a second current in a second path by a first current mirror. The second current includes the second set of leakage currents and a second write current. The first write current corresponds to the second write current. The first set of leakage currents corresponds to the second set of leakage currents.
Public/Granted literature
- US20220359010A1 MEMORY CELL ARRAY CIRCUIT AND METHOD OF FORMING THE SAME Public/Granted day:2022-11-10
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