- 专利标题: Method of planarizing insulating layer for memory device
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申请号: US16850591申请日: 2020-04-16
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公开(公告)号: US11587941B2公开(公告)日: 2023-02-21
- 发明人: Byung Woo Kang , Sae Jun Kwon , Hwal Pyo Kim , Jin Taek Park , Yang Seok Lim , Young Ock Hong
- 申请人: SK hynix Inc.
- 申请人地址: KR Icheon-si
- 专利权人: SK hynix Inc.
- 当前专利权人: SK hynix Inc.
- 当前专利权人地址: KR Icheon-si
- 代理机构: William Park & Associates Ltd.
- 优先权: KRKR10-2019-0101738 20190820
- 主分类号: H01L27/11556
- IPC分类号: H01L27/11556 ; H01L27/11582 ; H01L21/822 ; H01L21/762 ; H01L21/8234
摘要:
A method of manufacturing a semiconductor device includes forming a stacked structure including trenches having different depths, forming an insulating layer on the stacked structure to fill the trenches, and forming a plurality of protrusions located corresponding to locations of the trenches by patterning the insulating layer. The method also includes forming insulating patterns filling the trenches, respectively, by planarizing the patterned insulating layer including the plurality of protrusions.
公开/授权文献
- US20210057431A1 MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE 公开/授权日:2021-02-25
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