- 专利标题： Loading effect reduction through multiple coat-etch processes
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申请号： US17001382申请日： 2020-08-24
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公开(公告)号： US11387105B2公开(公告)日： 2022-07-12
- 发明人: Jin-Dah Chen , Ming-Feng Shieh , Han-Wei Wu , Yu-Hsien Lin , Po-Chun Liu , Stan Chen
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Haynes and Boone, LLP
- 主分类号： H01L21/306
- IPC分类号： H01L21/306 ; H01L21/283 ; H01L21/308 ; H01L21/8234 ; H01L29/49 ; H01L29/66 ; H01L29/78 ; H01L29/51
摘要：
First, second, and third trenches are formed in a layer over a substrate. The third trench is substantially wider than the first and second trenches. The first, second, and third trenches are partially filled with a first conductive material. A first anti-reflective material is coated over the first, second, and third trenches. The first anti-reflective material has a first surface topography variation. A first etch-back process is performed to partially remove the first anti-reflective material. Thereafter, a second anti-reflective material is coated over the first anti-reflective material. The second anti-reflective material has a second surface topography variation that is smaller than the first surface topography variation. A second etch-back process is performed to at least partially remove the second anti-reflective material in the first and second trenches. Thereafter, the first conductive material is partially removed in the first and second trenches.
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