- 专利标题: Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach
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申请号: US16912113申请日: 2020-06-25
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公开(公告)号: US11348919B2公开(公告)日: 2022-05-31
- 发明人: Nicole Thomas , Ehren Mannebach , Cheng-Ying Huang , Marko Radosavljevic
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Schwabe, Williamson & Wyatt, P.C.
- 主分类号: H01L27/092
- IPC分类号: H01L27/092 ; H01L29/06 ; H01L29/417 ; H01L29/423 ; H01L29/786 ; H01L21/02 ; H01L21/8238 ; H01L29/66
摘要:
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
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