An apparatus for video decoding includes processing circuitry. The processing circuitry is configured to receive a syntax element in a bit stream indicating a maximum number of merge candidates on a merge candidate list for a set of coding blocks, and receive a merge with motion vector difference (MMVD) flag syntax element in the bit stream indicating that an MMVD mode is used to generate a motion vector predictor of a current block included in the set of coding blocks. The processing circuitry is further configured to infer a base candidate index of the MMVD mode to be a predetermined value when the maximum number of the merge candidates is less than 2.