- 专利标题: Data-sampling integrity check using gated clock
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申请号: US16571255申请日: 2019-09-16
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公开(公告)号: US11244046B2公开(公告)日: 2022-02-08
- 发明人: Ziv Hershman
- 申请人: Nuvoton Technology Corporation
- 申请人地址: TW Hsin-chu
- 专利权人: Nuvoton Technology Corporation
- 当前专利权人: Nuvoton Technology Corporation
- 当前专利权人地址: TW Hsin-chu
- 代理机构: Kligler & Associates Patent Attorneys Ltd
- 主分类号: G06F21/55
- IPC分类号: G06F21/55 ; G06F1/08
摘要:
An electronic device includes clock generation circuitry, a combinational logic circuit, one or more functional state-sampling components, and protection logic. The clock generation circuitry is configured to generate a clock signal having a periodic clock cycle. The combinational logic circuit includes multiple internal nets and one or more outputs. The functional state-sampling components are configured to sample the respective outputs of the combinational logic circuit periodically in accordance with the clock signal. The protection logic is configured to receive one or more signals from the internal nets or outputs of the combinational logic circuit, to detect, in one or more of the received signals, a signal instability that occurs during a predefined portion of the periodic clock cycle in which, in accordance with a design of the combinational logic circuit, the signals are expected to be stable, and to initiate a responsive action in response to the detected signal instability.
公开/授权文献
- US20210081529A1 Data-Sampling Integrity Check using Gated Clock 公开/授权日:2021-03-18
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