- 专利标题： Partial writing method of dram memoryl device to reduce power consumption associated with large voltage swing of internal input/output lines
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申请号： US16868544申请日： 2020-05-07
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公开(公告)号： US11094372B1公开(公告)日： 2021-08-17
- 发明人: Yasuhiro Konishi , Yasuji Koshikawa
- 申请人： Powerchip Semiconductor Manufacturing Corporation
- 申请人地址： TW Hsinchu
- 专利权人： Powerchip Semiconductor Manufacturing Corporation
- 当前专利权人： Powerchip Semiconductor Manufacturing Corporation
- 当前专利权人地址： TW Hsinchu
- 代理机构： JCIPRNET
- 主分类号： G11C7/10
- IPC分类号： G11C7/10 ; G11C11/4096 ; G11C11/408 ; G11C11/4094 ; G11C11/4063
摘要：
A semiconductor memory and a partial writing method are provided. The semiconductor memory includes a memory bank, a write amplifier circuit, a plurality of input/output pins and a plurality of address pins. The write amplifier circuit is coupled to the memory bank through a plurality of internal input/output lines. The plurality of input/output pins are coupled to the write amplifier circuit through a plurality of input lines. A part of plurality of address pins receive a column address instruction, and at least one of another part of the plurality of address pins receive an operation code. The semiconductor memory determines a part of the internal input/output lines for transmitting input data according to the operation code, and operates the write amplifier circuit to perform a partial writing mode according to the operation code so as to write the input data into the memory bank according to the column address instruction.
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