- 专利标题: Compilation to reduce number of instructions for deep learning processor
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申请号: US16393333申请日: 2019-04-24
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公开(公告)号: US11093224B2公开(公告)日: 2021-08-17
- 发明人: Eri Ogawa , Kazuaki Ishizaki , Hiroshi Inoue
- 申请人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 代理机构: Tutunjian & Bitetto, P.C.
- 代理商 Randall Bluestone
- 主分类号: G06F9/45
- IPC分类号: G06F9/45 ; G06F8/41 ; G06F9/30
摘要:
A method performed during execution of a compilation process for a program having nested loops is provided. The method replaces multiple conditional branch instructions for a processor which uses a conditional branch instruction limited to only comparing a value of a general register with a value of a special register that holds a loop counter value. The method generates, in replacement of the multiple conditional branch instructions, the conditional branch instruction limited to only comparing the value of the general register with the value of the special register that holds the loop counter value for the inner-most loop. The method adds (i) a register initialization outside the nested loops and (ii) a register value adjustment to the inner-most loop. The method defines the value for the general register for the register initialization and conditions for the generated conditional branch instruction, responsive to requirements of the multiple conditional branch instructions.
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