发明授权
- 专利标题: Forming dual metallization interconnect structures in single metallization level
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申请号: US16364700申请日: 2019-03-26
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公开(公告)号: US11037875B2公开(公告)日: 2021-06-15
- 发明人: Hari P. Amanapu , Charan V. Surisetty , Raghuveer R. Patlolla
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Ryan, Mason & Lewis, LLP
- 代理商 James Nock
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L23/532 ; H01L23/528
摘要:
Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.
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