Invention Grant
- Patent Title: Multi-layer thyristor random access memory with silicon-germanium bases
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Application No.: US16914181Application Date: 2020-06-26
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Publication No.: US10978456B2Publication Date: 2021-04-13
- Inventor: Harry Luan
- Applicant: TC Lab, Inc.
- Applicant Address: US CA Gilroy
- Assignee: TC Lab, Inc.
- Current Assignee: TC Lab, Inc.
- Current Assignee Address: US CA Gilroy
- Agency: Aka Chan LLP
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L21/02 ; H01L29/74 ; H01L29/165 ; H01L29/10 ; H01L29/66

Abstract:
A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.
Public/Granted literature
- US20200328214A1 Multi-Layer Thyristor Random Access Memory with Silicon-Germanium Bases Public/Granted day:2020-10-15
Information query
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