Invention Grant
- Patent Title: Methods for integrated circuit design and fabrication
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Application No.: US16542790Application Date: 2019-08-16
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Publication No.: US10930505B2Publication Date: 2021-02-23
- Inventor: Tsong-Hua Ou , Ken-Hsien Hsieh , Shih-Ming Chang , Wen-Chun Huang , Chih-Ming Lai , Ru-Gun Liu , Tsai-Sheng Gau
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/033
- IPC: H01L21/033 ; H01L21/027 ; H01L21/321 ; H01L21/311 ; H01L21/3213

Abstract:
The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
Information query
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