- 专利标题: Zero padding apparatus for encoding variable-length signaling information and zero padding method using same
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申请号: US16360409申请日: 2019-03-21
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公开(公告)号: US10812105B2公开(公告)日: 2020-10-20
- 发明人: Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim
- 申请人: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- 申请人地址: KR Daejeon
- 专利权人: Electronics and Telecommunications Research Institute
- 当前专利权人: Electronics and Telecommunications Research Institute
- 当前专利权人地址: KR Daejeon
- 代理机构: NSIP Law
- 优先权: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@377b882f com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@cabbd51
- 主分类号: H03M13/00
- IPC分类号: H03M13/00 ; H03M13/11 ; H03M13/27 ; H03M13/29 ; H03M13/15 ; H03M13/25
摘要:
A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.
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