- 专利标题: Analog multiplexing scheme for decision feedback equalizers
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申请号: US16526433申请日: 2019-07-30
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公开(公告)号: US10785067B2公开(公告)日: 2020-09-22
- 发明人: Raghukiran Sreeramaneni , Daniel B. Penney
- 申请人: Micron Technology, Inc.
- 申请人地址: US ID Boise
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 当前专利权人地址: US ID Boise
- 代理机构: Fletcher Yoder, P.C.
- 主分类号: H04L25/03
- IPC分类号: H04L25/03 ; G11C7/10 ; H04L25/49 ; G11C7/02 ; G11C11/4096
摘要:
A device includes a voltage generator that generates a reference signal, a multi-level bias generator coupled to the voltage generator to receive the reference signal and generate a plurality of bias level signals based at least in part on the reference signal. The multi-level bias generator transmits the plurality of bias level signals to a plurality of multiplexers that each receive a select signal to select a subset of bias level signals of the plurality of bias level signals. The device also includes an adjustment circuit of a decision feedback equalizer that receives a respective selected subset of bias level signals from one multiplexer of the plurality of multiplexers and utilizes the respective selected subset of bias level signals to compensate for inter-symbol interference of a bit due to a previously received bit of a bit stream.
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