Invention Grant
- Patent Title: Controlling coarse pixel size from a stencil buffer
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Application No.: US16142866Application Date: 2018-09-26
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Publication No.: US10706591B2Publication Date: 2020-07-07
- Inventor: Karthik Vaidyanathan , Prasoonkumar Surti , Hugues Labbe , Atsuo Kuwahara , Sameer Kp , Jonathan Kennedy , Murali Ramadoss , Michael Apodaca , Abhishek Venkatesh
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- Main IPC: G06T11/00
- IPC: G06T11/00 ; G06T1/20 ; G06T1/60 ; G06T15/00

Abstract:
Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.
Public/Granted literature
- US20190087983A1 CONTROLLING COARSE PIXEL SIZE FROM A STENCIL BUFFER Public/Granted day:2019-03-21
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T11/00 | 2D〔二维〕图像的生成 |