A semiconductor storage device in an embodiment includes a memory cell array, a pad to which data is inputted, an ODT circuit connected to the pad, an ODT driver configured to drive the ODT circuit, and a control circuit configured to supply an enable signal and a resistance value control signal to the ODT driver. The pad is arranged between the memory cell array and a first end side of the semiconductor storage device, and the ODT circuit is arranged between the pad and the first end side. The ODT driver is arranged between the ODT circuit and the first end side. An ODT control signal line configured to transmit a resistance value control signal, and an ODT enable signal line configured to transmit an enable signal are arranged between the ODT driver and the first end side.