- 专利标题: Delay line with selectable delay
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申请号: US15974956申请日: 2018-05-09
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公开(公告)号: US10547295B2公开(公告)日: 2020-01-28
- 发明人: Robert Callaghan Taft , Vineethraj Rajappan Nair
- 申请人: Texas Instruments Incorporated
- 申请人地址: US TX Dallas
- 专利权人: TEXAS INSTRUMENTS INCORPORATED
- 当前专利权人: TEXAS INSTRUMENTS INCORPORATED
- 当前专利权人地址: US TX Dallas
- 代理商 John R. Pessetto; Charles A. Brill; Frank D. Cimino
- 主分类号: H03K5/14
- IPC分类号: H03K5/14 ; H03K5/00
摘要:
In described examples, an electronic circuit for delaying a signal (received at an input node) includes a delay line with multiple tap locations, a tap line proximate to the delay line and coupled to an output node, and multiple groups of switches. Switches in the groups of switches are severally coupled between tap locations corresponding to the respective group of switches, and the tap line. When the signal is propagated through the delay line, a first number of the switches corresponding to a selected tap location are closed, a second number of the switches corresponding to an adjacent tap location are closed, and the signal is transmitted with a delay through the closed switches, to the tap line, to the output node. The delay includes an average, weighted using the first and second numbers, of delays corresponding to the selected and adjacent tap locations.
公开/授权文献
- US20180337665A1 DELAY LINE WITH SELECTABLE DELAY 公开/授权日:2018-11-22
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