发明授权
- 专利标题： Method to reduce trap-induced capacitance in interconnect dielectric barrier stack
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申请号： US16237407申请日： 2018-12-31
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公开(公告)号： US10546742B2公开(公告)日： 2020-01-28
- 发明人: He Ren , Mehul B. Naik , Yong Cao , Yana Cheng , Weifeng Ye
- 申请人： Applied Materials, Inc.
- 申请人地址： US CA Santa Clara
- 专利权人： APPLIED MATERIALS, INC.
- 当前专利权人： APPLIED MATERIALS, INC.
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Patterson + Sheridan LLP
- 主分类号： H01L21/02
- IPC分类号： H01L21/02 ; H01L21/768
摘要：
The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.
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