An information processing device includes a memory, and a plurality of processor cores that access the memory. The plurality of processor cores respectively executes processes to be executed by the plurality of processor cores in accordance with execution priority levels of the processes. When a polling process for repeatedly determining whether reception data for input/output processing is received is underway in one of the plurality of processor cores, the plurality of processor cores respectively executes the input/output processing in response to a determination, made by the polling process, that the reception data have been received, and when the polling process is not underway in any of the plurality of processing cores, the plurality of processor cores respectively executes the input/output processing in response to a processor interrupt issued upon reception of the reception data.