发明授权
- 专利标题： Apparatus and method for bonding branch instruction with architectural delay slot
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申请号： US13789467申请日： 2013-03-07
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公开(公告)号： US10540179B2公开(公告)日： 2020-01-21
- 发明人: Ranganathan Sudhakar , Parthiv Pota
- 申请人： MIPS Tech, LLC
- 申请人地址： US CA Campbell
- 专利权人： MIPS Tech, LLC
- 当前专利权人： MIPS Tech, LLC
- 当前专利权人地址： US CA Campbell
- 代理机构： Adam Intellex, PLC
- 主分类号： G06F9/30
- IPC分类号： G06F9/30
摘要：
A processor is configured to identify a branch instruction immediately followed by an architectural delay slot. A single bonded instruction comprising the branch instruction immediately followed by the architectural delay slot is created. The single bonded instruction is loaded into an instruction buffer.
公开/授权文献
- US20140258694A1 Apparatus and Method for Branch Instruction Bonding 公开/授权日：2014-09-11
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