- 专利标题: Method and related apparatus for reducing gate-induced drain leakage in semiconductor devices
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申请号: US15992817申请日: 2018-05-30
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公开(公告)号: US10535752B2公开(公告)日: 2020-01-14
- 发明人: Kong-Beng Thei , Chien-Chih Chou , Hsiao-Chin Tuan , Yi-Huan Chen , Alexander Kalnitsky
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Eschweiler & Potashnik LLC
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L21/768 ; H01L29/78
摘要:
In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.
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