- 专利标题: Memory device with improved latency and operating method thereof
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申请号: US15599819申请日: 2017-05-19
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公开(公告)号: US10535395B2公开(公告)日: 2020-01-14
- 发明人: Soo-Ho Cha , Chankyung Kim , Sungchul Park , Kwangchol Choe
- 申请人: SAMSUNG ELECTRONICS CO., LTD.
- 申请人地址: KR Suwon-si, Gyeonggi-Do
- 专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人地址: KR Suwon-si, Gyeonggi-Do
- 代理机构: F. Chau & Associates, LLC
- 优先权: KR10-2016-0076694 20160620
- 主分类号: G11C7/00
- IPC分类号: G11C7/00 ; G11C11/408 ; G06F12/02 ; G11C5/06 ; G11C7/10 ; G11C11/4076 ; G11C11/4093 ; G11C11/4096
摘要:
Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.
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