- 专利标题: Metal gates of transistors having reduced resistivity
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申请号: US16191908申请日: 2018-11-15
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公开(公告)号: US10510596B2公开(公告)日: 2019-12-17
- 发明人: Chia-Ching Tsai , Yi-Wei Chiu , Li-Te Hsu
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater Matsil, LLP
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L29/66 ; H01L21/28 ; H01L29/78 ; H01L29/08 ; H01L29/49 ; H01L23/535 ; H01L23/532 ; H01L29/417 ; H01L29/51
摘要:
A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.
公开/授权文献
- US20190103311A1 Metal Gates of Transistors Having Reduced Resistivity 公开/授权日:2019-04-04
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